Presentation
A "Shift-Left" Analysis Flow For Layout Parasitics Of High Speed Analog Mixed Signal Design
DescriptionFor today's high speed AMS design, as the processes shrinking and design complexity increasing, the layout parasitics have become more and more important and even more dominant than devices, which impact a lot on design's performance.On the other hand, as the parasitics magnitude increase, it's more and more hard to debug complex parasitics issue through traditional method like post-sim, with which designer need to spend more post-sim and sign-off runtime, more experience-based manually debug and iteration to identify the real bottleneck can usually make the design schedule out of control.
To improve the design efficiency, a "shift-left" parasitic analysis flow for AMS layout parasitics become necessary and important, to help design identify the parasitics caused design problem more early, quickly, and easily.
Before go to sign-off stage, we first use ParagonX perform quickly parasitics analysis of R, C, RC delay, net matching, etc in early design stage, and debug result by element, by layer, by layout locations, to identify and optimize the real layout bottleneck, reducing the layout iterations ranging from weeks to hours. Through the flow improvement, we makes parasitics debugging and layout optimization easy and efficient, significantly improve design efficiency.
To improve the design efficiency, a "shift-left" parasitic analysis flow for AMS layout parasitics become necessary and important, to help design identify the parasitics caused design problem more early, quickly, and easily.
Before go to sign-off stage, we first use ParagonX perform quickly parasitics analysis of R, C, RC delay, net matching, etc in early design stage, and debug result by element, by layer, by layout locations, to identify and optimize the real layout bottleneck, reducing the layout iterations ranging from weeks to hours. Through the flow improvement, we makes parasitics debugging and layout optimization easy and efficient, significantly improve design efficiency.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP