Presentation
Memory Clusters – Divide the design and optimize MBIST insertion efforts
DescriptionProblem Statement : Modern applications demand memory intensive complex SOC's with tighter time to market schedules. For such designs; implementing high quality test and repair solution is a unique challenge to achieve with optimum mbist insertion efforts. Traditional MBIST insertion methods needs multiple MBIST insertion runs as many times as functional RTL or netlist changes. This keeps DFT team engaged running mbist insertion multiple times.
Approach/Methodology :
In this paper, we've broadly covered optimize design practices which helps reducing mbist insertion iterations. The design hierarchies are partitioned into memory clusters such a way that the mbist insertion is required only if there are memory changes in the given cluster. The flow is created such that the functional connections remains intact and only the bist pins of memories get hooked up to BIST logic. This avoids any mbist intercepts in functional paths. Different experiments are done to achieve optimum area, power, timing closure and bist runtimes.
When performing the DFT insertion flow with sub-blocks, you insert MemoryBIST and pre-DFT DRCs at the sub-block level and then move up to the sub-block's next parent physical block level (where the sub-block is instantiated) to perform ICL extraction/Synthesis/Scan insertion.
Impact/Results :
Multiple instantiations — You only need to perform the DFT insertion flow once for a sub-block. Thereafter, every instantiation of the sub-block includes the inserted DFT hardware
Small size — Most sub-blocks are not big enough to be considered their own physical regions which saves run time
Readiness — Sometimes the sub-block RTL is complete before the RTL for the physical layout region, thus you can begin DFT insertion on the sub-block as soon as RTL is ready
Approach/Methodology :
In this paper, we've broadly covered optimize design practices which helps reducing mbist insertion iterations. The design hierarchies are partitioned into memory clusters such a way that the mbist insertion is required only if there are memory changes in the given cluster. The flow is created such that the functional connections remains intact and only the bist pins of memories get hooked up to BIST logic. This avoids any mbist intercepts in functional paths. Different experiments are done to achieve optimum area, power, timing closure and bist runtimes.
When performing the DFT insertion flow with sub-blocks, you insert MemoryBIST and pre-DFT DRCs at the sub-block level and then move up to the sub-block's next parent physical block level (where the sub-block is instantiated) to perform ICL extraction/Synthesis/Scan insertion.
Impact/Results :
Multiple instantiations — You only need to perform the DFT insertion flow once for a sub-block. Thereafter, every instantiation of the sub-block includes the inserted DFT hardware
Small size — Most sub-blocks are not big enough to be considered their own physical regions which saves run time
Readiness — Sometimes the sub-block RTL is complete before the RTL for the physical layout region, thus you can begin DFT insertion on the sub-block as soon as RTL is ready
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP