Presentation
Design Automation of Minimal Layer Count Microprocessor 2.5D Silicon Interposer
DescriptionIntel latest microprocessors are built by chiplet assembly over Foveros passive silicon interposer. Second generation based on this technology was targeting a more aggressive cost optimization, featuring reduced interposer layer count and decoupling density. Stronger design automation flows were developed, minimizing the manual layout labor, and tuned to address the inherent challenges of reduced layer count interposer. The design automation flow consists of few key stages, some of them logistics and some carry the algorithms for the layout synthesis. Among those synthesis algorithms is voltage area automatic generation, which set the regions for power delivery grid stenciling and decoupling spread. Another algorithm is pad-to-pad robust via connectivity, enabled to withstand slight offsets between the interposer bumps, and to mediate the connectivity of the pad with the rest of the power delivery grid. Although some manual user interventions are allowed, and some manual or semi manual layout editing is recommended, all manual steps are registered and archived to allow automatic re-run iterations. Finally, the full database can be built within few hours of uninterrupted flow. The database is meeting all design criterions (manufacturing, reliability, timing), minimizing the need of manual layout design, and meeting schedule by the efficient run times.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP