Presentation
An Efficient Early Thermal Management Solution in 3DIC design
DescriptionMulti-die designs, 2.5DIC and 3DIC, have been rising in popularity in last decade as they offer tremendously increased levels of integration, smaller footprint, performance gains, and more. While they are attractive for many applications, it also creates more stringent design bottlenecks in the areas of thermal management and power delivery. For 3DICs, in addition to the complex SoC/PCB interactions seen in their 2D counterparts, we must account for electrical and thermal coupling between dies as well.
For these advanced package design, such as 2.5D/3DIC, chiplets, power, thermal, electromagnetics and mechanical – and their highly coupled interactions – are the primary limiters of entitled performance, yield and cost. As we know, when temperature increases, it increases the device leakage power consumption, and requires more cooling costs. Also, temperature increase can have tremendous negative impact on the overall design performance, such as interconnect resistance hike, device performance degradation, and the thermal induced noise can change the light wave phased in optical designs.
Higher thermal effects also cause reliability issues, like electromigration failure, aging issue, and stress related failures. So thermal management becomes very important to avoid thermal runaway and reliability issues. However, full 3DIC system thermal analysis with detail CTM takes too much time at sign-off stage, and once thermal issues arise, there is no space left to adjust on the SoC die. Therefore, in most cases, upgrading cooling equipment is almost the only option, and the cost is too high! We seek a shifting left method to manage chip thermal in the early stages. Early thermal management can more efficiently avoid thermal run away, reduce thermal management costs, and give designers more confidence during design sign-off analysis.
Thermal aware floorplan & power plan with preliminary collateral in RedHawk-SC-Electrothermal at early stage can analyze and predict power-thermal reliability issues, identify thermal issues early enables fixes/changes that can have a profound effect on reducing failures with a minimum of design effort. Through early-stage thermal-stress analysis, we can avoid the warpage and solder joint reliability issues caused by thermal expansion.
keywords : 3DIC, thermal-aware floorplan, power-plan, early-stage thermal management
For these advanced package design, such as 2.5D/3DIC, chiplets, power, thermal, electromagnetics and mechanical – and their highly coupled interactions – are the primary limiters of entitled performance, yield and cost. As we know, when temperature increases, it increases the device leakage power consumption, and requires more cooling costs. Also, temperature increase can have tremendous negative impact on the overall design performance, such as interconnect resistance hike, device performance degradation, and the thermal induced noise can change the light wave phased in optical designs.
Higher thermal effects also cause reliability issues, like electromigration failure, aging issue, and stress related failures. So thermal management becomes very important to avoid thermal runaway and reliability issues. However, full 3DIC system thermal analysis with detail CTM takes too much time at sign-off stage, and once thermal issues arise, there is no space left to adjust on the SoC die. Therefore, in most cases, upgrading cooling equipment is almost the only option, and the cost is too high! We seek a shifting left method to manage chip thermal in the early stages. Early thermal management can more efficiently avoid thermal run away, reduce thermal management costs, and give designers more confidence during design sign-off analysis.
Thermal aware floorplan & power plan with preliminary collateral in RedHawk-SC-Electrothermal at early stage can analyze and predict power-thermal reliability issues, identify thermal issues early enables fixes/changes that can have a profound effect on reducing failures with a minimum of design effort. Through early-stage thermal-stress analysis, we can avoid the warpage and solder joint reliability issues caused by thermal expansion.
keywords : 3DIC, thermal-aware floorplan, power-plan, early-stage thermal management
Event Type
Engineering Track Poster
TimeTuesday, June 255:18pm - 5:19pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP