Presentation
An effective Hierarchical Top Scope Signal EM Flow for closing Large SOC Designs
DescriptionThis study introduces an innovative approach for closing large SOC designs efficiently through an effective hierarchical EM flow. The methodology leverages hierarchical analysis framework, integrating both top-level and block-level EM considerations to address the complexities of large-scale SoC designs. This approach uniquely combines the granularity of block-level analysis with the holistic perspective of top-level integration, enabling precise identification and mitigation of EM issues without compromising the accuracy.
Key elements of this methodology include advanced EM modeling at various hierarchical levels, strategic partitioning of the SoC into manageable blocks, and the use of boundary models to accurately assess EM effects at interconnects.
The results demonstrate a significant reduction in the time required to close large SoC designs and memory footprint. This methodology not only enhances the reliability and performance of the SoC but also offers a scalable solution applicable to a wide range of complex integrated circuit designs. The hierarchical top scope signal EM flow represents a substantial advancement in SoC design methodologies, setting a new benchmark for efficiently addressing electromigration challenges in large-complex SoC designs.
Key elements of this methodology include advanced EM modeling at various hierarchical levels, strategic partitioning of the SoC into manageable blocks, and the use of boundary models to accurately assess EM effects at interconnects.
The results demonstrate a significant reduction in the time required to close large SoC designs and memory footprint. This methodology not only enhances the reliability and performance of the SoC but also offers a scalable solution applicable to a wide range of complex integrated circuit designs. The hierarchical top scope signal EM flow represents a substantial advancement in SoC design methodologies, setting a new benchmark for efficiently addressing electromigration challenges in large-complex SoC designs.
Event Type
Engineering Track Poster
TimeTuesday, June 255:19pm - 5:20pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP