Presentation
Bus Delay Skew Minimization for High Bandwidth Memory Designs
DescriptionHigh bandwidth memory (HBM) consists of several memory chips and a dedicated buffer die that serializes and de-serializes data for processing and transferring. One major parameter deciding the performance of a buffer die is the number of parallel signal buslines spanning half the die between signal IO circuitry (e.g., PHY) and input/output ports (i.e., through-silicon via (TSV)) of the buffer die. The speed of signal buses is also important to make smoother signal transitions during the clock cycle time. This transition time ensuring full signal swing, determines the maximum clock frequency of the HBM. The faster the device and the larger the number of buslines, the higher the performance an HBM can deliver. The busline bit count is expected to exceed several tens of thousands in the next HBM generation. The busline delay difference must be minimized for correct signal transfer of all bits within a very narrow available time slot for signal transition. Until now, the bus design has been done by iterative manual layout and simulation, since no good automated solutions exist.This work seeks an automated layout and optimization methodology for the many signal buslines for a next generation HBM. We formulate the design constraints from custom layouts, and develop a novel bus delay optimization algorithm based on a commercial P&R tool. This automated solution demonstrates a bus layout for an HBM buffer die within seconds, while satisfying all metric requirements.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP