Presentation
A Novel Methodology for Library Characterization and Modeling Considering Local Layout Effect
DescriptionLLE (Local Layout Effect) refers to the mutual influence of adjacent layout elements in semiconductor design. In the process of measuring the characteristics of standard cells, LLE context assumptions are stored in design kit together to be utilized for the block level analysis.To minimize LLE impact on design, conventional library characterization relies on assumption of fixed overlay patterns that takes into account worst or best context based on multiple experiments. But actual context and characterized context can be different, and those situations make uncertainty skew on clock path causing pessimism and optimism on design. This proposed characterization and modeling method resolves the gap between actual context and design kit due to assumption of fixed overlay patterns during characterization. It removes redundant pessimism and optimism in cell delay modeling, then achieved PPA improvement and higher sign-off frequency in design.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP