Presentation
A Heuristic-Based Routing Methodology for Block-Level Memory Layout Routability Enhancement
DescriptionAs the technology node shrinks, routing in memory devices is becoming a challenging problem. Advanced commercial routing solutions have been introduced for dealing with more complex design rules and less routing resources, however, routing results are still far from satisfactory. Complex routing patterns from those routing solutions are not meeting customer's specific expectations, rather making it more difficult for engineers to manually modify it. In this paper we explore the possibility whether a simpler approach, a heuristic-based routing methodology can be a better option for improving routability. Our routing methodology simplifies entire routing process into two stages: global routing and local routing, and heuristic-based algorithm is applied in each stage. With our routing methodology, we could achieve higher routing success rate by on average 43%, with less routing resource usage by on average 13% and less drc errors by on average 68%.
Event Type
Engineering Track Poster
TimeTuesday, June 255:18pm - 5:18pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP