Presentation
Die-Level Dynamic-IR Analysis Shift-Left Enabled by RedHawk-SC SigmaDVD
DescriptionAs Silicon scaling continue to reach into Angstrom domain, dimension scaling slows down. however silicon feature and compute power stills continue to increase at rate comparable to Moore's Law. Power Integrity is now becoming a key challenge for sub nanometer processes. Die-level Power Integrity signoff is normally done at the final stage of IC design. Power-Plan design and synthesis on the other hand are done before Automated-Place-And-Route (APR). A key conundrum for Power Plan design and synthesis, is the lack of reference information, especially for new IP, such as a latest high-performance CPU. A tapeout quality IR signoff for APR, requires a post-routed (final-stage) APR database, a couple of post-layout simulation pattern which exercises the logic to consume current from the on-die power-grid in a near-realistic worst-case manner, an optimized package model which describe the package ball to bump impedance. All three critical input information for IR analysis becomes available only at the end of the IC implementation process, posing risk to tapeout schedule and possible IC failures due to severe IR drop. In this presentation, we demonstrate how Sigma-DVD resolve this conundrum, allowing our engineers to identify Dynamic-IR hotspots, without end-of-the-stage functional pattern, and hence "shift-left" to strengthen Power-plan on potential weak-spots, before the weak-spots gets identifed too late in the implantation process.
Event Type
Engineering Track Poster
TimeMonday, June 245:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP