Presentation
Design Methodologies for Minimizing Local Routing Congestions in Low-level Metal Layers
DescriptionIn advanced technology node, the difference in the ratio of cell height scaling and interconnect scaling has resulted in local routing congestion in the low-level metal layers. This congestion is one of the bottleneck factors in node scaling. In this paper, we address two approaches to alleviate the local routing congestion in the low-level metal layers: (1) increasing pin access points by utilizing the middle-of-line (MOL) layer as a pin of the standard cell, and (2) minimizing local interconnections by merging repetitive logic combinations. We propose an efficient method for preparing the standard cells that offer routability gains, as well as equivalent cell swapping case by case that are expected to enhance routability during the placement and routing (P&R) stage. Our experiments show a 1.82% and 0.6% block area gain for MOL pin routing and merged logic cells, respectively. We demonstrate that alleviating local routing congestion in lower-level metal layers is an important key for interconnect scaling.
Event Type
Engineering Track Poster
TimeTuesday, June 255:13pm - 5:14pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP