Presentation
RDL and Bump Automation for Early EMIR Analysis In 2.5D, 3D and Single DIE Designs using RedHawk-SC Design ECO's
DescriptionIn order to achieve the targeted PPA goals in our Single Die/2.5D/3DIC designs, accurate early analysis is crucial for IR and timing optimization from beginning stage of the project.
In the beginning of the project cycle:
• RDL with BUMPs is not available, Full flat design hierarchy is not yet available.
• Bump currents cannot be checked very early in design cycle and cannot be optimized.
• IA/IB weakness cannot be caught as power sources will be created on IB/IA pins for block level runs.
• RDL DEF + block runs will be taking more computational resources.
• For 3DIC designs, TSV model and Back metal resistances will be missing in early EMIR analysis.
Our approach is by utilizing Redhawk-SC EMIR Tool Design ECOs, we can draw RDL and BUMPs in our design. This modified design with Virtual RDL and BUMPs is now used to perform IR and EM analysis. For 3DIC designs
• Accurate block level results by accounting TSV, Back Metal resistances in block level runs.
• Multiple Design of Experiments can be performed.
• Accurate Top-Die results are available by accounting Bottom die parasitics for block level runs which helps in Top-Die design planning.
Modelling these additional challenges accurately is important for accurate early analysis.
In the beginning of the project cycle:
• RDL with BUMPs is not available, Full flat design hierarchy is not yet available.
• Bump currents cannot be checked very early in design cycle and cannot be optimized.
• IA/IB weakness cannot be caught as power sources will be created on IB/IA pins for block level runs.
• RDL DEF + block runs will be taking more computational resources.
• For 3DIC designs, TSV model and Back metal resistances will be missing in early EMIR analysis.
Our approach is by utilizing Redhawk-SC EMIR Tool Design ECOs, we can draw RDL and BUMPs in our design. This modified design with Virtual RDL and BUMPs is now used to perform IR and EM analysis. For 3DIC designs
• Accurate block level results by accounting TSV, Back Metal resistances in block level runs.
• Multiple Design of Experiments can be performed.
• Accurate Top-Die results are available by accounting Bottom die parasitics for block level runs which helps in Top-Die design planning.
Modelling these additional challenges accurately is important for accurate early analysis.
Event Type
Engineering Track Poster
TimeTuesday, June 255:30pm - 5:30pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP