Presentation
Critical corners selection for standard cells LVF characterization using AI
DescriptionOn-chip variation (OCV) is a significant factor affecting timing sign-off for digital designs at 20nm and below. At lower technology nodes, timing measurements such as propagation delay, setup time, and hold time may change by 50%-100% due to statistical variation. In order to capture these variation effects accurately, timing .libs include variation modeling information defined by the Liberty Variation Format (LVF).
LVF requires that each timing data point must also perform a statistical simulation/Monte Carlo analysis in order to capture the full distribution of behavior. Each data point is not just a single additional table per timing arc. For each timing arc and nominal measurement (e.g. delays, transitions and constraints), there are up to 5 additional measurements used for statistical analysis: early and late 3-sigma values, mean shift, standard deviation and skewness. This increases the runtime for SPICE characterization exponentially.
In this paper, we discuss a methodology for reducing SPICE characterization runtime by identifying the critical corners to characterize and generate the remaining LVF data using AI.
LVF requires that each timing data point must also perform a statistical simulation/Monte Carlo analysis in order to capture the full distribution of behavior. Each data point is not just a single additional table per timing arc. For each timing arc and nominal measurement (e.g. delays, transitions and constraints), there are up to 5 additional measurements used for statistical analysis: early and late 3-sigma values, mean shift, standard deviation and skewness. This increases the runtime for SPICE characterization exponentially.
In this paper, we discuss a methodology for reducing SPICE characterization runtime by identifying the critical corners to characterize and generate the remaining LVF data using AI.
Event Type
Engineering Track Poster
TimeTuesday, June 255:10pm - 5:11pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP