Presentation
An Automated Solution for Streamlining Qualifications of Connectivity and DRC Across Diverse 3DIC Packaging Technologies
DescriptionThe integration of multiple dies and substrates into a unified 3D-IC package presents a compelling solution to the limitations posed by scaling and challenges in SOC migration, making it a focal point in semiconductor advancement. Despite its prominence, diverse fabrication methodologies, teams, and formats introduce complexities to seamless integration. This approach underscores the critical need for innovative approaches to ensure cohesive connectivity. Additionally, it emphasizes the imperative role of automation in generating 3D-IC rule decks for swift and precise qualification. Efficient qualification solutions demand automated systems capable of synthesizing rule decks while adhering to design specifications and manufacturing methods. This approach accelerates system netlist generation, layout assembly, and LVS (Layout vs. Schematic) rule deck creation, expediting physical verification to mitigate challenges, and promote seamless integration across diverse substrates in semiconductor design and manufacturing.
Event Type
Engineering Track Poster
TimeTuesday, June 255:35pm - 5:36pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP