Presentation
A Solution for Optimizing Customerized-MMB
DescriptionAs the proportion of memories increasing in design, MMB (Multi-Memory Bus) interface is widely used in HPC core for memory test, which is a predefined bus in Function RTL, providing an access to multiple memory arrays and no need for memory wrappers. As a result of MMB interface application, the test area, timing impact and routing congestion can be reduced. However, there are some challenges when using MMB interface. The memories inside MMB interface only support serially test which means test time, test cost and the chip time-to-market will increase.
In this paper, we propose some solution for above challenges.
The memory subgroups of one MMB interface will be tested parallelly, and the outputs of every two adjacent subgroups will make a comparison in-situ. In order to ensure the assuracy of the compare results, the output data of one subgroup will also feed into processor for comparation.
The repair logic is also shared between the parallel test subgroups. A common repair solution will be applied for the test groups.
In this paper, we propose some solution for above challenges.
The memory subgroups of one MMB interface will be tested parallelly, and the outputs of every two adjacent subgroups will make a comparison in-situ. In order to ensure the assuracy of the compare results, the output data of one subgroup will also feed into processor for comparation.
The repair logic is also shared between the parallel test subgroups. A common repair solution will be applied for the test groups.
Event Type
Engineering Track Poster
TimeTuesday, June 255:12pm - 5:13pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP