Presentation
Accelerating IO Liberty Generation through ML based Solution
DescriptionTime-to-market is a crucial factor in today's competitive chip design landscape. Accurate timing and power analysis are essential for successful tapeout, demanding fast and precise Liberty characterization data (.libs). Traditional methods, heavily reliant on SPICE simulations, are often time-consuming and resource intensive. This presentation investigates the application of AI to revolutionize library characterization in two different chip design scenarios.
Scenario 1 leverages ML to analyze existing PVT data and build accurate models for timing, power, and noise across various Liberty formats (NLDM, CCS, CCSN and LVF). This dramatically reduces characterization time for new PVT additions, offering up to a 100x runtime savings. Importantly, the generated .libs maintain high accuracy, with deviations from Spice simulations within 5% for timing & 10% for leakage power and internal power energy.
Scenario 2 optimizes the characterization flow by identifying a critical subset of .libs from existing libraries and generating the remaining .libs within a target accuracy range. This significantly reduces the need for recharacterization, saving over 50% of time and resources during Spice model updates or minor design changes.
Scenario 1 leverages ML to analyze existing PVT data and build accurate models for timing, power, and noise across various Liberty formats (NLDM, CCS, CCSN and LVF). This dramatically reduces characterization time for new PVT additions, offering up to a 100x runtime savings. Importantly, the generated .libs maintain high accuracy, with deviations from Spice simulations within 5% for timing & 10% for leakage power and internal power energy.
Scenario 2 optimizes the characterization flow by identifying a critical subset of .libs from existing libraries and generating the remaining .libs within a target accuracy range. This significantly reduces the need for recharacterization, saving over 50% of time and resources during Spice model updates or minor design changes.
Event Type
Engineering Track Poster
TimeTuesday, June 255:07pm - 5:07pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP