Presentation
Physical Design With Intelligence
DescriptionOptimizing chip Power, Performance, Area, Schedule, and Cost (PPASC) is crucial to stay competitive in today's rapidly evolving technological landscape. Optimal design PPASC, require designers to explore large design space of functional, physical and process parameters that have complex relationships amongst themselves and optimize designs for conflicting goals iteratively. The quality of results is highly dependent on engineering expertise and limited by schedule and cost priorities. AI techniques can augment physical design and optimization effort with capabilities for multi-objective design exploration, replace traditional iterative feedback cycles with data driven insights and automate manual tasks with pattern recognition capabilities. The use of AI in backend design can enhance efficiency, quality, reliability and have higher chance of reaching PPASC minima as compared to conventional methods.
In this talk we will discuss some of the application of AI in physical design for clock parameter tuning, place and route recipe generation, last mile PPASC optimization, design robustness analysis and design rule fixing and share preliminary results from design testcases. Results indicate measurable benefit in terms of PPASC, design quality and reliability. It also streamlines design process, ensure execution predictability and free-ups engineering resource for higher value tasks paving way for innovative, reliable, and improved PPASC chips that can shape the future of technology.
In this talk we will discuss some of the application of AI in physical design for clock parameter tuning, place and route recipe generation, last mile PPASC optimization, design robustness analysis and design rule fixing and share preliminary results from design testcases. Results indicate measurable benefit in terms of PPASC, design quality and reliability. It also streamlines design process, ensure execution predictability and free-ups engineering resource for higher value tasks paving way for innovative, reliable, and improved PPASC chips that can shape the future of technology.
Event Type
Engineering Track Poster
TimeTuesday, June 255:23pm - 5:24pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP