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Avoiding CDC bugs introduced during Synthesis Optimizations and Netlist Transformations
DescriptionDesign synthesis flows are not aware of Clock Domain Crossing (CDC). Thus, synthesis optimizations that are built to enhance power, performance, and area (PPA), may cause corruption in CDC paths and therefore, the netlist generated by the synthesis tools can introduce new CDC errors even after CDC signoff at the RTL.

The synthesis optimizations may also cause functional glitch issues due to retiming, self-gating, and mux-decompositions which can result in silicon escapes.
Currently, designers use ad hoc methods such as manual synthesis constraints, full CDC re-verification at gate-level, or relying on Gate-level Simulation (GLS) to overcome these challenges. However, it is error prone due to over-constraining, high noise-level during re-verification, or low GLS coverage.

Using VC SpyGlass CDC-aware Fusion Compiler flow, correct-by-construction synthesis is performed with regard to avoiding CDC bugs during netlist transformation.
Running this automated flow using the following steps:
• After RTL CDC signoff using VC SpyGlass CDC, a Static database is generated to guide the synthesis
• Fusion Compiler generates synthesis constraints using the Static database to ensure no corruption happens to CDC paths and no functional glitches are introduced

Integrating this technology in the flow mitigates the risk of introducing any new CDC violations in Netlist that were previously qualified at RTL.
Event Type
Engineering Track Poster
TimeTuesday, June 255:48pm - 5:48pm PDT
LocationLevel 2 Exhibit Hall
Topics
Back-End Design
Embedded Systems
Front-End Design
IP