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Advancing Power Signoff for High Speed ΔΣADC
DescriptionContinuous Time Delta Sigma Modulators (CTDSMs) are critical part of various RF receiver chains. These ADCs should be able to accommodate wider signal bandwidths with high dynamic range. This requires higher sampling rate leading to increased power consumption. Thereby, making successful power and signal integrity sign-off a challenging task.

In EMIR analysis, a circuit is simulated together with the parasitic resistor and capacitor network which models the IR drop and Electromigration (EM) effects for both power and signal nets. Advanced node designs have more complex EM rules and with exponential increase in parasitics (RCs) for such kind of designs, the EM simulation becomes more costly.

To address these challenges, we have used Virtuoso-ADE and SpectreX-EMIR solution which handles high-capacity designs and provides exceptional performance. With this flow, a new two-stage iterated method of Spectre-X is used for EMIR analysis to achieve golden accuracy with high performance gain.

In this paper, by using this new two stage iterated method of Spectre-X EMIR, we have achieved close to golden accuracy of direct method (single stage), accelerating EMIR signoff analysis closure by 2.5X performance gain. Seamless integration of Voltus-Fi solution with easy visualization and postprocessing features of ADE, provides productivity gain of 30%.
Event Type
IP
TimeTuesday, June 2510:30am - 10:45am PDT
Location2010, 2nd Floor
Topics
Engineering Tracks
IP