Presentation
Technology and IP Scaling Beyond 5nm
DescriptionThis session addresses the frontiers of technology scaling, examining the interplay between cost, performance, and power as designers navigate current limitations and future trends. Discussions will range from the evolution of process technology, such as FinFET to GAA, to the strategic use of DTCO and disaggregated designs in overcoming die size and cost-per-transistor challenges. Emphasizing the critical role of packaging in adopting chiplets, advances in interconnect and 3D-IC technologies will be explored. The collective insights aim to chart a course through the complexities of scaling in the more-than-Moore era, focusing on economic and technological viability.
Event Type
IP
TimeTuesday, June 251:30pm - 3:00pm PDT
Location2008, 2nd Floor
Engineering Tracks
IP