Presentation
Generative AI for Chip Design: Game Changer or Damp Squib?
DescriptionGenerative AI (GenAI) technologies for modalities including text, image, speech etc., are poised for huge practical impact in a range of industries. How will GenAI impact the EDA business, and perhaps conversely, does EDA have a role to play in advancing GenAI? Recent results suggest GenAI can indeed play a transformative role across the design flow from chip specification and verification, to pre- and post-silicon test, physical design and design for manufacturability, thereby improving designer productivity, time-to-market and design quality. Conversely, EDA can play a crucial role in addressing the massive training and inference costs of state-of-art trillion parameter or more GenAI models via pruning, specialization and acceleration. The panel will seek to address several key questions the about the role of GenAI and EDA namely:
(1) Can GenAI design a full chip? Intentionally provocative, panelists will be asked whether GenAI methods alone, or with limited supervision, can translate natural language design intent to high-quality GDSII, along with test and verification procedures? What role will human expertise, experience and intuition play in a GenAI driven flow, and which parts can be truly automated? In sum, what are the killer applications for GenAI in chip design?
(2) Specialized vs. general-purpose foundation models for chip design? Generalized foundation models like GPT-4, Bard etc. have shown exceptional abilities to generalize to unseen tasks, including potentially RTL code and EDA script generation. Will these massive foundation models suffice or do we need smaller and specialized foundation models for hardware design? Specialized models can improve performance on hardware=-specific tasks, in addition to having manageable training and inference costs.
(3) Open- vs. closed-sourced datasets and models for hardware? Many semiconductor companies have massive internal datasets that can be used to train foundation models for hardware, but these models will likely not be released publicly due to IP issues. Unlike for software, open datasets of hardware are scarce—for example, Verilog is only 0.004% of the code on GitHub. Are there avenues for training large open-source GenAI models for chip design, or do we expect these models to be internal and/or black-boxed?
(4) Regulatory, legal, safety and robustness issues? The recent Executive Order by the Biden administration requires, amongst other things, the development of " standards, tools, and tests to help ensure that AI systems are safe, secure, and trustworthy." What does this mean for GenAI models in the EDA context? Models trained on open-source datasets must additionally worry about copyright and IP violation issues, user privacy and the ``right to be forgotten" and additional concerns about inadvertent or malicious backdoors in ML models.
(1) Can GenAI design a full chip? Intentionally provocative, panelists will be asked whether GenAI methods alone, or with limited supervision, can translate natural language design intent to high-quality GDSII, along with test and verification procedures? What role will human expertise, experience and intuition play in a GenAI driven flow, and which parts can be truly automated? In sum, what are the killer applications for GenAI in chip design?
(2) Specialized vs. general-purpose foundation models for chip design? Generalized foundation models like GPT-4, Bard etc. have shown exceptional abilities to generalize to unseen tasks, including potentially RTL code and EDA script generation. Will these massive foundation models suffice or do we need smaller and specialized foundation models for hardware design? Specialized models can improve performance on hardware=-specific tasks, in addition to having manageable training and inference costs.
(3) Open- vs. closed-sourced datasets and models for hardware? Many semiconductor companies have massive internal datasets that can be used to train foundation models for hardware, but these models will likely not be released publicly due to IP issues. Unlike for software, open datasets of hardware are scarce—for example, Verilog is only 0.004% of the code on GitHub. Are there avenues for training large open-source GenAI models for chip design, or do we expect these models to be internal and/or black-boxed?
(4) Regulatory, legal, safety and robustness issues? The recent Executive Order by the Biden administration requires, amongst other things, the development of " standards, tools, and tests to help ensure that AI systems are safe, secure, and trustworthy." What does this mean for GenAI models in the EDA context? Models trained on open-source datasets must additionally worry about copyright and IP violation issues, user privacy and the ``right to be forgotten" and additional concerns about inadvertent or malicious backdoors in ML models.
Organizer
Moderator
Event Type
Research Panel
TimeTuesday, June 253:30pm - 5:30pm PDT
Location3014, 3rd Floor
AI
EDA