Presentation
WinoGen: A Highly Configurable Winograd Convolution IP Generator for Efficient CNN Acceleration on FPGA
DescriptionThe convolution neural network (CNN) has been widely adopted in computer vision tasks.
In the FPGA-based CNN accelerator design, Winograd convolution can effectively improve computation performance and save hardware resources.
However, building efficient and highly compatible IP for arbitrary Winograd convolution on FPGA remains underexplored.
To address this issue, we propose a novel and efficient reformulation of Winograd convolution, named Structured Direct Winograd Convolution (SDW).
We further develop WinoGen, a Chisel-based highly configurable Winograd convolution IP generator.
Given arbitrary input/output tile size and kernel size, it can generate optimized high-performance IP automatically.
Meanwhile, our generated IP can be compatible with multiple kernel sizes and tile sizes.
Experimental results show that the IP generated by WinoGen achieves DSP efficiency up to 3.80 GOPS/DSP and energy efficiency up to 652.77 GOPS/W while showing 2.45 times and 3.10 times improvements when processing a same CNN model compared with state-of-the-arts.
In the FPGA-based CNN accelerator design, Winograd convolution can effectively improve computation performance and save hardware resources.
However, building efficient and highly compatible IP for arbitrary Winograd convolution on FPGA remains underexplored.
To address this issue, we propose a novel and efficient reformulation of Winograd convolution, named Structured Direct Winograd Convolution (SDW).
We further develop WinoGen, a Chisel-based highly configurable Winograd convolution IP generator.
Given arbitrary input/output tile size and kernel size, it can generate optimized high-performance IP automatically.
Meanwhile, our generated IP can be compatible with multiple kernel sizes and tile sizes.
Experimental results show that the IP generated by WinoGen achieves DSP efficiency up to 3.80 GOPS/DSP and energy efficiency up to 652.77 GOPS/W while showing 2.45 times and 3.10 times improvements when processing a same CNN model compared with state-of-the-arts.
Event Type
Research Manuscript
TimeTuesday, June 253:45pm - 4:00pm PDT
Location3012, 3rd Floor
Design
SoC, Heterogeneous, and Reconfigurable Architectures