Presentation
High Coverage QA for Process Variability Compensation in LVS Rule Deck
DescriptionManufacturing of semiconductor designs pass through many complex steps, among which is process variabilities compensation that is applied to the layout geometries as selective edge bias to improve the yield of the products. Biasing layout polygons will impact the resistance and capacitances of the layout and thus the parasitic extraction step needs to be aware of this bias values, moreover, the final polygons after bias must not result in a design rule violation and must not change the circuitry topology of the design. A biasing algorithm typically involves modifying the dimensions and/or positions of the polygons to ensure that they meet the design rules and are manufacturable. Implementing the bias algorithm correctly is critical to ensure correct compensation and manufacturability. This paper presents an automated QA method to assure bias is implemented correctly, thus ensuring downstream manufacturing processes are applied to a correct layout. This solution introduces the LVS Retarget Checker designed for this purpose. The proposed method provides high coverage and enhancing the reliability of PDK (Process Design Kit), and elevating the overall quality of the design.
Event Type
Engineering Track Poster
TimeTuesday, June 255:47pm - 5:48pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP