Presentation
Heterogeneous 3DIC Multi Voltage Timing Signoff
DescriptionCross die paths in 3DIC requires many additional signoff corner analysis compared to conventional 2DIC signoff corners owing to different possible conditions at each die level. In case of multi voltage 3DIC interface, signoff corners need to be coupled with 3DIC voltage scenarios in order to create complete multi voltage signoff scenarios. 3DIC simultaneous multi voltage analysis compresses the voltage scenarios per unique 3DIC process/temp/BEOL combinations, which in turn reduces no. of analysis corners and helps in reducing compute requirement. Dominant corner selection approach helps further limit the analysis corners and reduce the overall compute requirement. Context derived from 3DIC multi voltage timing analysis can be used as voltage scenario specific I/O budget (min/max) to die level 2DIC Timing analysis in order to optimize the setup/hold timing of 3DIC interface
Configurable delay cells added on 3DIC interface paths can be used for silicon tuning of 3DIC interface paths
Configurable delay cells added on 3DIC interface paths can be used for silicon tuning of 3DIC interface paths
Event Type
Engineering Track Poster
TimeTuesday, June 255:51pm - 5:52pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP