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Session

Late Breaking Results Poster: Late Breaking Results Posters
Event TypeLate Breaking Results Poster
TimeWednesday, June 266:00pm - 7:00pm PDT
LocationLevel 2 Lobby
Presentations
Late Breaking Results: Power Rail Routing for Advanced Multi-Layered Printed Circuit Boards
Late Breaking Results: Coulomb Force-Based Routability-Driven Placement Considering Global and Local Congestion
Late Breaking Results: Machine Learning Based Reference Ripple Error Suppression in Successive Approximation Register Analog-to-Digital Converters
Late Breaking Results: TriSC: Low-Cost Design of Trigonometric Functions with Quasi Stochastic Computing
Late Breaking Results: Routability-Driven FPGA Macro Placement Considering Complex Cascade Shape and Region Constraints
Late Breaking Results: Circuit-Algorithm Co-design for Learnable Audio Analog Front-End
Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration
Late Breaking Results: Fast System Technology Co-Optimization Framework for Emerging Technology Based on Graph Neural Networks
Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI)
Late Breaking Results: Differential and Massively Parallel Sampling of SAT Formulas
Late Breaking Results: Evaluation of Human Action Quality with Linear Recurrent Units and Graph Attention Networks on Embedded Systems.
Author Informations
Late Breaking Results: On the One-Key Premise of Logic Locking
Late Breaking Result: AQFP-aware Binary Neural Network Architecture Search
Late Breaking Results: Extracting QNNs from NISQ Computers via Ensemble Learning
Author Informations
Late Breaking Results: A real-time diffusion-based filter for human pose estimation on edge devices
Mixed-Cell-Height Detailed Placement under Multi-Cell Spacing Constraints
Late Breaking Results: Language-level QoR modeling for High-Level Synthesis
Late Breaking Results: Wiring Reduction for Field-coupled Nanotechnologies
Late Breaking Results: Modern Automatic PCB Placement with Complex Constraints
Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification